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6:18:42
hayley
Well, I sent an email to Cliff Click asking about what he thought about callee saved registers, and I expected to not get a response any time soon. I was amazingly proved wrong.
6:23:27
hayley
The context was the "Bits of advice for VM writers" presentation, where he is also critical of callee-saves registers on x86 <https://www.youtube.com/watch?v=vzzABBxo44g>. I asked if he thought inlining (or call site optimization) changes the assumptions made, and if he thinks callee-saves is a good idea on x86-64 or ARM.
6:24:49
hayley
He said callee-saves was very messy in concurrent stack scanning on HotSpot, and "it wasn't really worth it for all the very-low-frequency GC bugs that entailed." And that callee-saves can sometimes get a small win on x86-64, because spilling is optimized. But on a RISC there is a larger win.
6:25:36
hayley
But, as he said it was "since leaf routines make up (nearly by definition) 50% of all calls", I wonder if I didn't communicate that I was interested in how these change under inlining.
6:36:00
hayley
I have sent a reply asking if he would change his mind with inlining, as our (some of the SICL developers) hypothesis is that there would be fewer but larger leaf functions under inlining or call site optimization.
7:30:56
moon-child
I wonder if https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/cheri-faq.html would be useful for implementing barriers
7:31:31
moon-child
though I'm not sure the extent to which it's available on production hardware; it has apparently been ported to riscv