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3:26:04
tich
I was reading "The RISC-V Reader" so that I can find out more about RISC-V and what to do in Cluster
3:27:01
beach
The instruction database for RISC-V in Cluster will be very simple I think. At least compared to the one for x86.
3:28:57
tich
Well Patterson keeps saying the ISA is elegant. all the RV32I instructions fit on half a page
3:30:38
tich
It is very compact and I think we would need different terminology or a new define-instruction macro all together
3:31:37
hayley
The operands, especially immediate values, have strange positions in instructions. The motivation is to make instruction decoding faster.
3:31:53
hayley
I suppose "disassembling hex dumps of machine code in your head" is not a situation in which "programs are written to be read" holds, and it is more elegant if you are designing hardware.
3:38:25
tich
Well noted I think the ISA designers wanted something not so difficult to implement in hardware
3:44:03
beach
The input is a sequence of objects where an object is either an instruction or a label. And instructions and labels are instances of some class.
9:58:12
beach
YAY, I think we now have a working definition of SUBTYPEP loaded into E5 as part of bootstrapping!
13:07:36
beach
With SUBTYPEP in place, I should be able to implement MAKE-ARRAY. Eclector also needs ADJUST-ARRAY which may be a bit tricky, but it shouldn't be too bad.
13:09:48
beach
Again, I think that once we have Eclector, we should concentrate on code generation and creating an initial executable from what we have. It will have a RPL instead of a REPL, but it will allow us to debug tons of stuff without the evaluator.