7:37:30beachI think at some point I need to implement some arbitrary code into instruction descriptors of Cluster. The x86 has some legacy restrictions. For instance, the one I ran into this morning is that PUSH with encoding 50+rd in 64-bit mode, can only handle the first 8 registers.
7:38:50beachI think the only way to handle situations like this is to introduce a test function that will check the operands that are requested, and return a Boolean indicating whether the descriptor applies or not.
7:39:36beachFor now, I think I'll just comment out those descriptors.
11:49:28froggeypush (and pretty much all other instructions) support using a rex prefix to extend the register field. PUSH R10 => 41 (rex.b) 52 (50+rd)
11:49:44froggeybut I think there are still a few odd cases you'll need to reject. iirc high byte registers (ah, ch, dh, bh) don't mix well with the extended registers, and I'm sure there are other examples
11:51:02beachI don't see it in the Intel documentation.
11:51:18beachBut maybe there is a general phrase somewhere.
11:54:26froggey"REX.B either modifies the base in the ModR/M r/m field or SIB base field; or it modifies the opcode reg field used for accessing GPRs." from section 2.2.1.2 "More on REX Prefix Fields" in volume 2 (my copy is a little old, so section numbers might not match up exactly)