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9:22:31
beach
I am making great progress on register allocation today. It looks like I figured out how to do normal argument processing also for the top-level ENTER-INSTRUCTION.
9:22:36
beach
After I figured that out, I have been fixing some bugs in the module that handles what I call an "arrangement", i.e., a data structure that, for each live lexical location, contains its attribution of stack slot and register number (if any).
9:22:42
beach
This data structure will also be useful in the form of a table in the code object, because it will tell the garbage collector which stack slots and registers contain Common Lisp objects that must be traced. It is not quite complete for that purpose yet, but it's a start.
9:22:43
beach
Anyway, now I am attacking some complicated instructions such as FIXNUM-DIVIDE. I dread reading the Intel documentation for DIV, because I know it is going to be messy.
9:23:35
moon-child
the main thing that's annoying is that it's a single divmod operation, so it clobbers two registers
9:24:54
beach
Right, so I have to create some special protocol functions ensuring those two are free.
9:25:39
moon-child
div is expensive enough that it might be worth just spilling whatever happens to be there
9:26:30
no-defun-allowed
A stowaway from the original 8086, which put the same outputs in AX and DX.
9:26:54
moon-child
the original 8086 didn't really have 'general purpose registers'. Most registers had a special purpose
9:27:06
moon-child
ax was the accumulator, cx the counter, di and si the source and destination indices
9:27:28
beach
Later, I might consider including those specific registers in my EDU computation, so that they will be less likely to be attributed if they are going to have to be available soon.
9:35:19
beach
We can always hope that this architecture will be a distant memory before I get around to that, though.
10:32:44
splittist
Of course. Just after they fix the makefile format and the ACM abandons two-column paper format.
13:51:24
beach
So the FIXNUM-DIVIDE-INSTRUCTION has two inputs and two outputs. I want the first input to be in RAX and the second input in anything but RAX or RDX, and I want RDX to be unattributed.
13:51:25
beach
Then I want the first output to be in RDX and the second output to be in RAX. So I need to start by checking whether the second input has a register attributed to it. And if it is either RAX or RDX, I need to move it to a different register. etc, etc.
13:52:06
beach
Maybe I should look for an existing RISC-V to x86 translator in the spirit of what DEC did for VAX to Alpha.
13:55:46
beach
AHA! "rv8: a high performance RISC-V to x86 binary translator" by Michael Clark and Bruce Hoult.
15:49:48
beach
I don't understand the question. At the moment SICL is just an end-user application. The registers that are visible to end-user applications can all be used.
18:09:22
beach
ebrasca: Very quickly (I am off for today). First x86-64, just because that's what I have. I hope to be able to acquire a RISC-V machine in the not-too-far future, so that would be an obvious one. I think for the other architectures, I will rely on other people to write and support backends.
18:30:39
ebrasca
pjb: IBM did also open they architecture, here one https://www.raptorcs.com/TALOSII/