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4:12:14
Bike
does sbcl's SSE stuff actually work? it's exported from sb-ext but not mentioned in the manual that i could see
4:13:29
no-defun-allowed
I was able to get cl-simd to work...eventually. I forgot what patches that needed, but it also needed an older SBCL where effective addresses had sizes.
4:15:29
no-defun-allowed
heisig was also working on sb-simd, which might become a SBCL contrib package one day. Until then, it's somewhat possible to fake it with clever use of general purpose instructions; that's what the code I put in SICL does, and that is also what the "fallback" for the Abseil hash table does.
4:16:27
no-defun-allowed
(The "Probing" section has such code; which is not far off what's in SICL now.)
4:50:16
no-defun-allowed
beach: Would it be okay if I clarified that I have only implemented non-concurrent hash tables so far in the letter I am sending to university (eventually)? I can send back my changes if you'd like to check them.
4:51:22
beach
That's fine, you can do it. Just make sure the style is consistent, like US spelling and such.
4:54:03
no-defun-allowed
I say "eventually" as enrolment hasn't worked for almost a week now; even when classes start next Monday.
4:57:40
no-defun-allowed
The enrolment procedure has me pick a plan (of which there are two, I am picking the older one as the courses seem more similar to those at my old university) and then allows me to pick class times to attend.
5:00:26
no-defun-allowed
The credit form also states that the university will ensure I won't have debts from, or have fail marks for, courses I have applied for credit for, should I submit it before classes start. But that is impossible at this rate.
5:03:55
no-defun-allowed
That, and the servers got cracked. Now I read they hope to have it fixed by tomorrow.
8:08:06
beach
Register allocation is a lot messier than I had imagined. Not because of the basic idea, but because of the large number of cases possible just to allocate a register. I will try to simplify a bit today, so that I can make progress.
9:32:47
beach
On page 93 and a bit on page 94 of http://metamodular.com/SICL/sicl-specification.pdf I now think I have a description of how to allocate a register for the second operand of a typical instruction of the type r <- r op s, given a MIR instruction of the type c <- a op b. Please let me know whether this description is understandable.
9:36:03
beach
The abstractions are "allocate a new register", "relatively soon", and "far in the future".
9:44:41
no-defun-allowed
I finished a SIMD implementation of my metadata protocol (using a somewhat modified cl-simd), and it's about 20% faster than the bit-trickery reference implementation. sb-sprof suggests that there is a lot of time spent in readers.
9:49:02
no-defun-allowed
The fact that it at least works suggests that the internal protocol for the linear-probing hash table is reasonable, so I may look at beginning to write the concurrent version tomorrow.
10:00:20
beach
Actually, put off reading that section. I think I am close to finishing the entire thing, and I changed the names of the variables.
14:33:18
beach
I think I finished the description of register allocation (given that we have computed EDU). It is on pages 91-95 of http://metamodular.com/SICL/sicl-specification.pdf in case someone has the time to have a look.
14:34:24
beach
There are so many cases that it is might happen that some case that occurs infrequently is wrong, or implemented incorrectly. So I am inclined to make the rules simpler in an initial implementation.