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Sunday, 22nd of September 2019, 10:51:39 UTC
10:51:51
stassats
aeth: mips 64, sparc 64, truly 64-bit alpha
10:52:11
stassats
there's plenty of time to waste on dead architectures!
10:55:06
stassats
and of course there's itanium, for the very adventurous
10:55:57
stassats
i'm talking dead, not decomposed
11:06:14
no-defun-allowed
PDP10 port when?
11:11:45
stassats
no-defun-allowed: not enough RAM
11:14:26
no-defun-allowed
Oh, more RAM, you need a ZX Spectrum then.
18:39:24
aeth
If Itanium really is as hard as it sounds, then porting compilers to Itanium will be the new retro challenge in 20 years or so when the 00s are retro instead of the 80s
18:40:27
pfdietz
I want to see an implementation exploiting ARM64's pointer tagging.
18:40:37
stassats
or we can just keep ignoring itanium, like it never happened
18:41:07
pfdietz
The Russian Elbrus also has tagged pointers, I've been told.
18:41:23
stassats
pfdietz: doesn't seem useful
18:43:03
stassats
storing the widetag there? we store more than just the widetag in the header word
18:43:26
stassats
the only benefit is possibly a bit quicker type checking
18:44:33
stassats
some small objects might get better alignment and be smaller
18:45:19
stassats
those that take up an even number of words, complex-double, ratios
18:50:04
stassats
but, without a widetag the gc won't know what to do
18:50:25
stassats
so, no space savings, just type checking benefits
19:12:43
karlosz
riscv without threads passes all but 1 test not related to the lack of floating trap hardware
19:12:49
karlosz
if i remember correctly
19:13:16
karlosz
still waiting for the price of a board to drop from 1k
19:33:58
aeth
why is PPC64 marked as in progress on the platform-table, but not RISC V? http://www.sbcl.org/platform-table.html
19:34:22
karlosz
aeth: nobody has riscv hardware, but techincally it should work in emulators
19:34:33
karlosz
idk how to update the platform table
19:34:40
karlosz
otherwise i would do it
19:34:43
aeth
I've been waiting on https://www.lowrisc.org/ for several years now at this point
19:35:09
aeth
I was going to look into a port when something like that got released, but you (I guess?) beat me to it by not waiting for hardware :-p
19:35:19
karlosz
crazy idea for arm32 threads: fix NIL to be some smallish integer (< 16 bits, maybe)
19:35:49
karlosz
and allocate all TLS regions to have NIL as the low pointer bits
19:36:07
karlosz
recover NIL just by taking the low bits of thread-tn
19:36:30
karlosz
aeth: its a little painful to port not on hardware
19:36:50
karlosz
if you want to port though, there are lots of platforms
19:38:17
aeth
of the list that stassats gave, only mips 64 sounds somewhat mainstream, although idk if it's used at all
19:38:42
aeth
alpha, sparc, etc., are platforms of dead unixes... same with itanium, actually.
19:38:44
karlosz
i mean, everything red in that table is more mainstream than a riscv chip
19:39:16
karlosz
why not add threads to riscv?
19:39:43
karlosz
those are major features i haven't done yet
19:39:49
karlosz
or get 32 bit riscv up and running
19:40:17
karlosz
i tried to keep the port building on both, but some 64-bit assumptions might have crept in
19:40:22
karlosz
the heavy lifting is done though
19:40:30
karlosz
since i originally wrote the port to be 32 bit
19:40:38
karlosz
although i only had a 64 bit vm
19:42:55
aeth
afaik 32 bit risc v is primarily embedded and the consumer boards with useful extras like division are probably going to be 64 bit
19:43:39
stassats
karlosz: i had a different idea about NIL, have it immediate encodable
19:43:50
stassats
as arm32 has crazy immediate encodings
19:46:46
karlosz
that would work too, if it were possible to encode nil like that
19:46:59
karlosz
it just needs to be able to point into static space, right?
19:47:33
stassats
it is possible to encode it, and even some other static symbols
19:47:58
karlosz
by immediate encodable, you mean it fits in an instruction?
19:48:25
karlosz
i don't know 32 bit arm architecture that well, but im surprised that nil got its own register in the first place if thats the case
19:48:35
karlosz
arm port log may have clues...
19:50:07
stassats
nil serves as on offset to other stuff
19:50:23
karlosz
to static symbols and funs
19:50:56
karlosz
so, what, it'd take an instruction to load nil into a scratch register, then do a load off of it
19:51:11
stassats
0x1000000B is encodable
19:51:29
karlosz
with what you say, it would be an instruction of overhead to access static stuff
19:51:59
karlosz
and no overhead to do compare and branch off nil
Sunday, 22nd of September 2019, 22:51:39 UTC