freenode/#mezzano - IRC Chatlog

15:53:27 fittestbits__ froggey: I did some research and looked through linux code some and found out they use the mfence instruction for a dma write barrier. This seems to work.

15:54:08 fittestbits__ I've added all three of the "fence" instructions: sfence, lfence and mfence to cpu.lisp. I'll include that as part of my commit/PR.

15:55:05 fittestbits__ However, I haven't been able to figure out the equivalent ARM code for mezzano. The instruction is "dmb oshst".

15:55:45 fittestbits__ That is, I haven't been able to figure out how to create a function that runs that instruction.

15:59:07 fittestbits__ In supervisor/x86-64/cpu.lisp, I've added functions: lfence, mfence, sfence and dma-write-barrier. We probably want only to use names that are not instruction specific.

15:59:31 fittestbits__ So maybe keep dma-write-barrier and get rid of the other?

16:35:19 froggey fittestbits__: that's interesting

16:35:35 froggey I'd have expected virtualbox to be completely coherent, but I guess not...

16:36:46 froggey for ARM it looks like you'd have to define the dmb instruction in compiler/lap-arm64.lisp, but don't worry as the arm64 port has bitrotted a little

16:37:53 froggey and just dma-write-barrier

16:38:46 fittestbits__ Yeah, that's what I was thinking too. Don't really want CPU specific APIs.

16:39:24 fittestbits__ I'll clean up cpu.lisp before I do the commit.

16:39:56 froggey alright